Dynamic random access memory (DRAM) devices provide a relatively inexpensive way to provide a large system memory. DRAM devices are relatively inexpensive because, in part, as compared to other memory technologies, a typical single DRAM cell consists only of two components: an access transistor and a capacitor. The access transistor is typically a metal oxide (MOS) transistor having a gate, a drain, and a source, as will be understood by those skilled in the art. The capacitor, which stores a high or low voltage representing high and low data bits, respectively, is coupled between the drain of the access transistor and a cell plate charged to Vcc/2. The gate of the access transistor is coupled to a word line and the source is coupled to a digit line. Thus, activating the word line turns on the transistor, coupling the capacitor to the digit line and thereby enabling data to be read from the DRAM cell by sensing the voltage at the digit line. Data is written to the DRAM cell by applying a desired voltage to the digit line.
DRAM technology is an inherently transitory nature storage technology. As is well known in the art, the storage capability of the DRAM cell is transitory in nature because the charge stored on the capacitor leaks. The charge can leak, for example, across the plates of the capacitor or out of the capacitor through the access transistor. The leakage current through a MOS transistor is an unwanted current flowing from drain to source even when the gate-to-source voltage of the transistor is less than the threshold voltage, as will be understood by those skilled in the art. As a result, DRAM cells must be refreshed many times per second to preserve the data stored. The refresh process being repeated many times per second, consuming an appreciable quantity of power. In portable systems, obtaining the longest life out of the smallest possible battery is a crucial concern, and, therefore, reducing the need to refresh memory cells to reduce power consumption is highly desirable.
The need to refresh memory cells can be reduced by reducing current leakage through the access transistor by increasing the threshold voltage of the access transistor. The semiconducting materials comprising the DRAM cells can be doped to increase the threshold voltage to activate the transistor from a typical level of 0.6 volts to 1.0 or more volts. Increasing the threshold voltage, because of the field effects in the MOS transistors used in typical DRAM cells, reduces the magnitude of current leakage through the access transistor. This is true because, as will be understood by those skilled in the art, when the polarity of the applied gate-to-source voltage causes the transistor to turn OFF, current decreases as the difference between the applied gate-to-source-voltage and threshold voltage increase. Thus, for a given voltage applied on a word line to turn OFF the corresponding access transistors, an increase in the threshold voltage will decrease the leakage current of the transistor for that word line voltage.
Increasing threshold voltage to suppress current leakage, however, becomes a less optimal solution as memory cells are reduced to fit more and more memory cells on a single die. This is because, for example, miniaturization of memory cells results in cell geometries that render the cells vulnerable to damage as higher voltages are applied.
Instead of increasing the threshold voltage of the access transistor and leaving the applied word line voltage the same, leakage current can be reduced by increasing the magnitude of the gate-to-source voltage that is applied to turn OFF the access transistor and leaving the threshold voltage of the transistor the same. Thus, instead of applying zero volts on the word line to turn OFF an NMOS access transistor, a negative voltage of 0.3 volts is applied to the word line, decreasing the transistor's current leakage for a given threshold voltage.
This approach is utilized in prior art word line drivers as shown in FIG. 1, which shows a prior art negative word line driver circuit 100. The word line driver 100 drives an active word line signal 124 to a voltage of 3.0 volts, Vccp, supplied to the word line driver 100 at Vccp supply line 104. The word line driver 100 drives the word line signal 124 inactive to a voltage of −0.3 volts, Vwln (voltage word line negative), supplied to the word line driver 100 at Vwln supply line 108. The word line driver 100 receives three inputs, PC* (precharge low enable), RAn, and RBout* (low enabled), with both RAn and RBout* being row predecoded addressing signals. The output of the word line driver 100 is the word line signal 124.
In operation, the word line signal 124 goes inactive when PC* is driven low. PC* going active turns ON PMOS transistor 136, thereby applying a high voltage Vccp to transistor 132, coupling the word line signal 124 to Vwln. At the same time, turning ON PMOS transistor 136 drives node 112 high, turning OFF PMOS transistor 144, while the low signal on the word line signal 124 turns ON transistor 140, which keeps node 112 high to keep transistor 132 turned ON independent of the signal carried on PC*.
On the other hand, the word line signal 124 goes active when PC* is driven high, turning OFF PMOS transistor 136. Then, when RAn is driven high, transistor 128 is turned ON, and when RBout* is driven low, node 112 goes low, applying a low signal to transistor 132 and decoupling the word line signal 124 from Vwln. Node 112 going low also turns ON PMOS transistor 144, coupling Vccp to the word line signal 124. The word line signal 124 going high turns OFF PMOS transistor 140, decoupling Vccp from the gate of transistor 132, keeping the word line signal 124 from being coupled to Vwln.
However, for the prior art word line driver 100 to effectively drive Vwln to the memory arrays the word line driver 100 directs, a significant Vwln negative voltage pump or negative voltage supply must be provided. This is problematic, because while the die is provided with Vcc and ground, Vwln typically must be provided within the device itself. As will be appreciated by one skilled in the art, supplying an appreciable Vwln current consumes space on the die, and also wastes power and capacity in generating a negative voltage source of suitable capacity.
Moreover, as is understood by one skilled in the art, a single word line driver circuit 100 is only one of many driver circuits that may be used in a memory array. Memory arrays may comprise thousands of rows of memory cells. Accordingly, the power and space consumption problems involved in a single die are compounded many times over when considering the power and space consumed in a memory system comprising a large memory array.
What is needed is a way to maintain the potential difference between the active word line signal and the inactive word line signal to reduce access transistor current leakage, while at the same time reducing the demand for a large negative voltage source.